1. Field of the Invention
The present invention relates to a semiconductor device of a chip-on-chip (CoC) type, and a method for manufacturing the same.
2. Description of the Related Art
Recently, with miniaturization and higher functionality of an electronic device, a study has been conducted on the semiconductor device of the CoC type which includes a plurality of semiconductor chips having penetration electrodes.
Concerning a method for manufacturing the semiconductor device of the CoC type, there is known a method for sequentially stacking a plurality of semiconductor chips having penetration electrodes on a wiring board or a support board, filling gaps among the semiconductor chips with underfillers, and then sealing the plurality of semiconductor chips with a resin to cover the entire chips including the underfillers.
A configuration of such a semiconductor device of a CoC type is described in, for example, Japanese Patent Application Laid-Open No. 2007-36184 (hereinafter, “Patent Document”).
The semiconductor device disclosed in the Patent Document has a structure where a plurality of semiconductor chips are stacked on a wiring board, the semiconductor chips are electrically connected to each other by penetration electrodes respectively formed on the semiconductor chips, and the penetration electrodes are exposed from a surface of the semiconductor chip disposed on a top stage. This structure results in generation of stress during expansion or contraction of the penetration electrodes due to a temperature change in the manufacturing process. Maximum stress is applied on a penetration electrode portion of the semiconductor chip disposed on the top stage, generating cracks in the semiconductor chip disposed on the top stage.